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general description the ds3508 is a programmable 8-channel gamma volt- age generator with one byte of on-chip eeprom and one byte of sram memory per channel. each channel is composed of an independent 8-bit dac with an asso- ciated eeprom/sram pair. at power-up, nonvolatile (nv) eeprom gamma data is loaded into its corre- sponding sram register that drives the associated 8-bit dac. an on-chip control register allows selectable con- trol of writing to sram/eeprom or sram only. the ds3508 is designed for low-power operation and draws less than 2ma (typ) from the v dd supply. programming occurs through an i 2 c-compatible serial interface with support for speeds up to 400khz. applications tft-lcd gamma buffer industrial controls features ? 8-bit gamma dacs, 8 channels ? 1 byte eeprom and 1 byte sram per channel ? ultra-low power (2ma i dd , typ) ? 400kbps i 2 c interface ? 9.0v to 15.5v analog supply ? 2.7v to 5.5v digital supply ? 20-pin tssop package ? address pin allows two ds3508s to reside on the same i 2 c bus ds3508 i 2 c, 8-channel gamma buffer with eeprom ________________________________________________________________ maxim integrated products 1 ordering information rev 1; 3/08 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. + denotes a lead-free package. t&r = tape and reel. part temp range pin-package DS3508E+ -45 c to +95 c 20 tssop DS3508E+t&r -45 c to +95 c 20 tssop top view ds3508 17 4 gm3 a0 18 3 gm2 gnd 19 2 gm1 sda 20 1v cc scl 14 7 gm6 vlm 15 6 gm5 vhm 13 8 gm7 vll 12 9 gm8 v dd 11 10 n.c. n.c. 16 5 gm4 vhh tssop pin configuration ds3508 v cc sda scl a0 gnd gm1 gm2 gm3 gm4 gm5 gm6 gm7 gm8 vll vlm v dd 15.0v vhm 8.0v 8 vhh 14.8v 7.0v 0.2v 5.0v i 2 c master source driver liquid-crystal display typical operating circuit
ds3508 i 2 c, 8-channel gamma buffer with eeprom 2 _______________________________________________________________________________________ absolute maximum ratings recommended operating conditions (t a = -45? to +95?) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. voltage range on v dd and vhh relative to gnd ..........................................-0.5v to +16v voltage range on vhm, vlm, and vll relative to gnd............................................-0.5v to +12v voltage range on v cc , sda, scl, and a0 relative to gnd ............................................-0.5v to +6.0v junction temperature ......................................................+125 c operating temperature range ...........................-45 c to +95 c programming temperature range .........................0 c to +70 c storage temperature.........................................-55? to +125? soldering temperature ..............................................refer to the ipc/jedec j-std-020 specification. parameter symbol conditions min typ max units analog supply voltage v dd (note 1) +9.0 +15.5 v vhh, vhm applies to gm1Cgm4 v dd /2 - 1 v dd - 0.2 v vlm, vll applies to gm5Cgm8 0.2 v dd /2 + 1 v vhhCvhm and vlmCvll v ref 3.0 v digital voltage supply v cc (note 1) 2.7 5.5 v input logic 0 (a0, sda, scl) v il 0.3 x v cc v input logic 1 (a0, sda, scl) v ih 0.7 x v cc v input electrical characteristics (v cc = +2.7v to +5.5v, t a = -45? to +95?.) parameter symbol conditions min typ max units analog supply current i dd v dd = 15.5v (note 2) 2 4 ma digital supply current, nv read or write i cc f scl = 400khz 0.2 1.0 ma digital supply standby current i stby v cc = 5.5v (note 3) 2 10 a input leakage (sda, scl, a0) i il v cc = 5.5v -1 +1 a input resistance at vhh, vhm, vlm, vll r in 1 m
ds3508 i 2 c, 8-channel gamma buffer with eeprom _______________________________________________________________________________________ 3 output electrical characteristics (v cc = +2.7v to +5.5v; v dd = 15.5v, t a = -45? to +95?, unless otherwise noted.) parameter symbol conditions min typ max units gamma dac resolution 8 bits integral nonlinearity error t a = +25c (note 4) -1.25 +1.25 lsb differential nonlinearity error t a = +25c (note 5) -0.5 +0.5 lsb output voltage range: gm1Cgm4 vhm vhh v output voltage range: gm5Cgm8 vll vlm v r out (gm1Cgm8) r out (notes 6, 7) 20 k amplifier offset t a = +25c (note 8) -35 +35 mv i 2 c electrical characteristics (v cc = +2.7v to +5.5v, t a = -45? to +95?, timing referenced to v il(max) and v ih(min) .) (figure 4) parameter symbol conditions min typ max units scl clock frequency f scl (note 9) 0 400 khz low period of scl t low measured at v il 1.3 s high period of scl t high measured at v ih 0.6 s bus free time between stop and start conditions t buf 1.3 s start setup time t su:sta scl rising through v ih to sda falling through v ih 0.6 s hold time (repeated) start condition t hd:sta sda falling through v il to scl falling through v ih 0.6 s data hold time t hd:dat 0 0.9 s data setup time t su:dat 100 ns a0 setup time t su:a before start 0.6 s a0 hold time t hd:a after stop 0.6 s sda and scl rise time t r (note 10) 20 + (0.1 x c b ) 300 ns sda and scl fall time t f (note 10) 20 + (0.1 x c b ) 300 ns stop setup time t su:sto 0.6 s sda and scl capacitive loading c b (note 10) 400 pf eeprom write time t w (note 11) 20 ms scl falling edge to sda output data valid t aa scl falling through v il to sda exit 0.3C0.7 x v cc window 900 ns output data hold t dh scl falling through v il until sda in 0.3C0.7 x v cc window 0 ns
ds3508 i 2 c, 8-channel gamma buffer with eeprom 4 _______________________________________________________________________________________ i 2 c electrical characteristics (continued) (v cc = +2.7v to +5.5v, t a = -45? to +95?, timing referenced to v il(max) and v ih(min) .) (figure 4) parameter symbol conditions min typ max units 4ma sink current 0.4 sda output low voltage v ol 6ma sink current 0.6 v input capacitance on a0, sda, or scl c i 5 10 pf nonvolatile memory characteristics (v cc = +2.7v to +5.5v) parameter symbol conditions min typ max units eeprom write cycles t a = +70c 50,000 writes note 1: all voltages referenced to ground. note 2: analog supply current specified with no load on gmx outputs. note 3: istby specified for the inactive state measured with sda = scl = v cc . note 4: inl = [v(gmx) i - (v(gmx) 0 ]/lsb(ideal) - i, for i = 0 to 254. note 5: dnl = [v(gmx) i+1 - (v(gmx) i ]/lsb(ideal) - 1, for i = 0 to 255. note 6: dac code = 80h. note 7: outputs unloaded. note 8: vhh = 12.0v, vhm = 8.75v, vlm = 6.75v, vll = 0.5v. note 9: timing shown is for fast-mode (400khz) operation. this device is also backward compatible with i 2 c standard mode. note 10: c b ?otal capacitance of one bus line in picofarads. note 11: eeprom write begins after a stop condition occurs. digital supply standby current vs. digital supply voltage ds3508 toc01 v cc (v) i cc stby current ( a) 1 2 3 4 5 6 7 8 9 10 0 5.5 5.0 4.0 4.5 3.0 3.5 2.5 2.0 6.0 sda = scl = v cc digital supply standby current vs. temperature ds3508 toc02 temperature ( c) i cc stby current ( a) 75 55 15 35 -5 -25 1 2 3 4 5 6 7 8 9 10 0 -45 95 v cc = 5.5v sda = scl = v cc analog supply current vs. analog supply voltage ds3508 toc03 v dd (v) i dd current (ma) 14 12 10 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 816 typical operating characteristics (v dd = 15.0v, v cc = 5.0v, t a = +25?, unless otherwise noted.)
ds3508 i 2 c, 8-channel gamma buffer with eeprom _______________________________________________________________________________________ 5 analog supply current vs. temperature ds3508 toc04 temperature ( c) i dd current (ma) 75 55 -25 -5 15 35 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 -45 95 gamma output vs. setting ds3508 toc05 gamma setting (dec) gm output (v) 224 192 160 128 96 64 32 3 6 9 12 15 0 0 256 gm1?m4 gm5?m8 v dd = 15.0v vhh = 14.8v vhm = 8.0v vlm = 7.0v vll = 0.2v gamma offset vs. temperature ds3508 toc06 temperature ( c) gm offset (mv) 75 55 15 35 -5 -25 -8 -6 -4 -2 0 2 4 6 8 10 -10 -45 95 gm1 = vhh = 14.5v gm1 = vhh = 12.0v gm8 = vlm = 8.5v gm8 = vll = 0.5v gm1 = vhm = 6.5v gm1 dnl ds3508 toc07 gamma setting (dec) gm1 dnl (lsb) 224 192 32 64 96 128 160 -0.75 -0.50 -0.25 0 0.25 0.50 0.75 1.00 -1.00 0 256 v dd = 15.0v vhh = 14.8v vhm = 8.0v gm1 inl ds3508 toc08 gamma setting (dec) gm1 inl (lsb) 224 192 32 64 96 128 160 -0.75 -0.50 -0.25 0 0.25 0.50 0.75 1.00 -1.00 0 256 v dd = 15.0v vhh = 14.8v vhm = 8.0v gm8 dnl ds3508 toc09 gamma setting (dec) gm8 dnl (lsb) 224 192 32 64 96 128 160 -0.75 -0.50 -0.25 0 0.25 0.50 0.75 1.00 -1.00 0 256 v dd = 15.0v vlm = 7.0v vll = 0.2v gm8 inl ds3508 toc10 gamma setting (dec) gm8 inl (lsb) 224 192 32 64 96 128 160 -0.75 -0.50 -0.25 0 0.25 0.50 0.75 1.00 -1.00 0 256 v dd = 15.0v vlm = 7.0v vhm = 0.2v typical operating characteristics (continued) (v dd = 15.0v, v cc = 5.0v, t a = +25?, unless otherwise noted.)
ds3508 i 2 c, 8-channel gamma buffer with eeprom 6 _______________________________________________________________________________________ functional diagram ds3508 eeprom 1 sram 1 gm1 8-bit dac eeprom 2 sram 2 gm2 8-bit dac eeprom 3 sram 3 gm3 8-bit dac eeprom 4 i 2 c interface control logic control registers sram 4 gm4 8-bit dac vhh sda scl a0 v dd vhm vll vlm v dd gnd v cc v cc eeprom 5 sram 5 gm5 8-bit dac eeprom 6 sram 6 gm6 8-bit dac eeprom 7 sram 7 gm7 8-bit dac eeprom 8 sram 8 gm8 8-bit dac
ds3508 i 2 c, 8-channel gamma buffer with eeprom _______________________________________________________________________________________ 7 pin description pin name type function 1 scl input serial clock input. i 2 c clock input. 2 sda input/ output serial data input/output (open drain). i 2 c bidirectional data pin that requires a pullup resistor to realize high logic levels. 3 gnd ground ground 4 a0 input address input. determines i 2 c slave address. 5 vhh reference input high-voltage dac, upper reference 6 vhm reference input high-voltage dac, lower reference 7 vlm reference input low-voltage dac, upper reference 8 vll reference input low-voltage dac, lower reference 9 v dd power analog supply 10, 11 n.c. no connection 12 gm8 13 gm7 14 gm6 15 gm5 output gamma analog outputs 5C8. these pins are the low-voltage gamma outputs referenced to vll and vlm. 16 gm4 17 gm3 18 gm2 19 gm1 output gamma analog outputs 1C4. these pins are the high-voltage gamma outputs referenced to vhh and vhm. 20 v cc power digital supply detailed description the ds3508 provides eight independent dacs that allow precise and repeatable setting of gamma curves. the ds3508 provides four high-voltage dacs (gm1?m4) that operate between vhh and vhm and four low-voltage dacs (gm5?m8) that operate between vlm and vll. each of the dacs provides 8 bits of resolution. the ds3508 dac output voltages are independently controlled by the data stored in that channel? sram register. the mode bit in the volatile control register (cr bit 7) determines how i 2 c data is written to the sram and eeprom gamma data registers. reading and writing to the sram/eeprom gamma data regis- ters is based on the state of the mode bit as follows: mode = 0: i 2 c writes to memory addresses 00h?7h write to both sram 1? and eeprom 1?. i 2 c reads from addresses 00h?7h read from sram 1?. mode = 1: i 2 c writes to addresses 00h?7h write to sram 1?. i 2 c reads from addresses 00h?7h read from sram 1?. regardless of the mode bit setting, all i 2 c reads of address 00?7h return the contents of the sram regis- ters. setting mode = 1 allows for quick writing of sram without the added delay of writing to the associated eeprom register. the data that is stored in eeprom and sram remains unchanged if the mode bit is toggled.
ds3508 i 2 c, 8-channel gamma buffer with eeprom 8 _______________________________________________________________________________________ on power-up, the gamma data that is stored in each channel? eeprom register is loaded into the corre- sponding sram registers. the volatile cr register pow- ers up as 00h, setting the device into mode 0. dac description the dacs are composed of a resistor string array and a switching network per channel. a high-voltage array with end points vhh and vhm controls outputs gm1?m4, and a low-voltage array with end points vlm and vll controls outputs gm5?m8. the resistor string arrays are composed of 255 identical resistors. the switching networks can select any tap point between adjacent resistors as well as either end point (vhh/vhm or vlm/vll pins). table 1 shows the rela- tionship between the 8-bit data and the dac voltage. eeprom sram gmx 8-bit dac i 2 c interface sda scl a0 figure 1. single-channel block diagram vhh vhm code 0 r h1 code 1 r h254 code 254 r h255 code 255 code 2 code 253 r h2 r h3 r h253 vll vlm code 0 r l1 code 1 r l254 code 254 r l255 code 255 code 2 code 253 r l2 r l3 r l253 figure 2. dac block diagram
slave address byte and address pin the slave address byte consists of a 7-bit slave address plus a r/ w bit (see figure 3). the ds3508? slave address is determined by the state of the a0 pin. this pin allows up to two devices to reside on the same i 2 c bus. connecting a0 to gnd results in a 0 in the corresponding bit position in the slave address. conversely, connecting a0 to v cc results in a 1 in the corresponding bit position. for example, the ds3508? slave address byte is e8h when a0 is grounded. i 2 c communication is described in detail in the i 2 c serial interface description section. ds3508 i 2 c, 8-channel gamma buffer with eeprom _______________________________________________________________________________________ 9 table 1. dac voltage/data relationship for selected codes output voltage data (binary) gm1Cgm4 gm5Cgm8 0000 0000 vhh vll 0000 0001 vhh + 1 x (vhm - vhh)/255 vll+ 1 x (vlm - vll)/255 0000 0010 vhh + 2 x (vhm - vhh)/255 vll + 2 x (vlm - vll)/255 0000 0011 vhh + 3 x (vhm - vhh)/255 vll + 3 x (vlm - vll)/255 0000 1111 vhh + 15 x (vhm - vhh)/255 vll + 15 x (vlm - vll)/255 0011 1111 vhh + 63 x (vhm - vhh)/255 vll + 63 x (vlm - vll)/255 0111 1111 vhh + 127 x (vhm - vhh)/255 vll + 127 x (vlm - vll)/255 1111 1101 vhh + 253 x (vhm - vhh)/255 vll + 253 x (vlm - vll)/255 1111 1110 vhh + 254 x (vhm - vhh)/255 vll + 254 x (vlm - vll)/255 1111 1111 vhm vlm 11 0 1 r/w a0 0 1 msb lsb read/write bit slave address* *the slave address is determined by address pin a0. figure 3. ds3508 slave address byte
ds3508 memory organization memory description the list of registers/memory contained in the ds3508 is shown in the memory map (table 2). each of the gmx registers also has a corresponding nv eeprom regis- ter. additional information regarding reading and writ- ing the memory is located in the i 2 c serial interface description section. i 2 c, 8-channel gamma buffer with eeprom 10 ______________________________________________________________________________________ table 2. memory map name address (hex) sram eeprom gm1 00 sram1 (8 bits) eeprom1 (8 bits) gm2 01 sram2 (8 bits) eeprom2 (8 bits) gm3 02 sram3 (8 bits) eeprom3 (8 bits) gm4 03 sram4 (8 bits) eeprom4 (8 bits) gm5 04 sram5 (8 bits) eeprom5 (8 bits) gm6 05 sram6 (8 bits) eeprom6 (8 bits) gm7 06 sram7 (8 bits) eeprom7 (8 bits) gm8 07 sram8 (8 bits) eeprom8 (8 bits) control register 08 volatile control register n/a reserved 09Cff reserved reserved detailed register description register 08h: control register (cr) power-up default 00h memory type volatile 08h mode reserved reserved reserved reserved reserved reserved reserved bit 7 bit 0 bit 7 mode 0 = (default) i 2 c writes to both sram and eeprom. mode 1 = i 2 c writes to sram only. bits 6 to 0 reserved. this bit determines if data is written to eeprom and sram or only sram. *all eeprom1? is factory-programmed to 80h.
i 2 c serial interface description i 2 c definitions the following terminology is commonly used to describe i 2 c data transfers. (see figure 4 and the i 2 c electrical characteristics table for additional information.) master device: the master device controls the slave devices on the bus. the master device generates scl clock pulses and start and stop conditions. slave devices: slave devices send and receive data at the master? request. bus idle or not busy: time between stop and start conditions when both sda and scl are inactive and in their logic-high states. start condition: a start condition is generated by the master to initiate a new data transfer with a slave. transitioning sda from high to low while scl remains high generates a start condition. stop condition: a stop condition is generated by the master to end a data transfer with a slave. transitioning sda from low to high while scl remains high generates a stop condition. repeated start condition: the master can use a repeated start condition at the end of one data trans- fer to indicate that it will immediately initiate a new data transfer following the current one. repeated starts are commonly used during read operations to identify a spe- cific memory address to begin a data transfer. a repeat- ed start condition is issued identically to a normal start condition. bit write: transitions of sda must occur during the low state of scl. the data on sda must remain valid and unchanged during the entire high pulse of scl plus the setup and hold time requirements. data is shifted into the device during the rising edge of the scl. bit read: at the end of a write operation, the master must release the sda bus line for the proper amount of setup time before the next rising edge of scl during a bit read. the device shifts out each bit of data on sda at the falling edge of the previous scl pulse and the data bit is valid at the rising edge of the current scl pulse. remember that the master generates all scl clock puls- es, including when it is reading bits from the slave. acknowledge (ack and nack): an acknowledge (ack) or not acknowledge (nack) is always the 9th bit transmitted during a byte transfer. the device receiving data (the master during a read or the slave during a write operation) performs an ack by transmitting a 0 during the 9th bit. a device performs a nack by trans- mitting a 1 during the 9th bit. timing for the ack and nack is identical to all other bit writes. an ack is the acknowledgment that the device is properly receiving data. a nack is used to terminate a read sequence or indicates that the device is not receiving data. byte write: a byte write consists of 8 bits of information transferred from the master to the slave (most signifi- cant bit first) plus a 1-bit acknowledgment from the slave to the master. the 8 bits transmitted by the mas- ter are done according to the bit write definition and the acknowledgment is read using the bit read definition. ds3508 i 2 c, 8-channel gamma buffer with eeprom ______________________________________________________________________________________ 11 sda scl t hd:sta t low t high t r t f t buf t hd:dat t su:dat repeated start t su:sta t hd:sta t su:sto t sp stop note: timing is referenced to v il(max) and v ih(min) . start figure 4. i 2 c timing diagram
ds3508 byte read: a byte read is an 8-bit information transfer from the slave to the master plus a 1-bit ack or nack from the master to the slave. the 8 bits of information that are transferred (most significant bit first) from the slave to the master are read by the master using the bit read definition, and the master transmits an ack using the bit write definition to receive additional data bytes. the master must nack the last byte read to terminate communication so the slave returns control of sda to the master. slave address byte: each slave on the i 2 c bus responds to a slave address byte sent immediately fol- lowing a start condition. the slave address byte con- tains the slave address in the most significant 7 bits and the r/ w bit in the least significant bit. the ds3508? slave address is determined by the state of the a0 address pin as shown in figure 3. an address pin connected to gnd results in a 0 in the correspond- ing bit position in the slave address. conversely, an address pin connected to v cc results in a 1 in the cor- responding bit positions. when the r/ w bit is 0 (such as in e8h), the master is indicating that it will write data to the slave. if r/ w = 1 (e9h in this case), the master is indicating that it wants to read from the slave. if an incorrect slave address is written, the ds3508 assumes the master is communicating with another i 2 c device and ignores the communication until the next start condition is sent. memory address: during an i 2 c write operation, the master must transmit a memory address to identify the memory location where the slave is to store the data. the memory address is always the second byte trans- mitted during a write operation following the slave address byte. i 2 c communication see figure 5 for i 2 c communication examples. writing a single byte to a slave: the master must gen- erate a start condition, write the slave address byte (r/ w = 0), write the memory address, write the byte of data, and generate a stop condition. remember the master must read the slave? acknowledgment during all byte write operations. when writing to the ds3508, the dac adjusts to the new setting following a stop. the eeprom (used to make the setting nv) is written following the stop condition at the end of the write command if the mode bit is set to 0. writing multiple bytes to a slave: to write multiple bytes to a slave in one transaction, the master gener- ates a start condition, writes the slave address byte (r/ w = 0), writes the starting memory address, writes up to 4 data bytes, and generates a stop condition. the ds3508 can write 1 to 4 bytes (1 page or row) in a single write transaction. this is internally controlled by an address counter that allows data to be written to consecutive addresses without transmitting a memory address before each data byte is sent. the address counter limits the write to one 4-byte page. the first page begins at address 00h and the second page begins at 04h. attempts to write to additional pages of memory without sending a stop condition between pages results in the address counter wrapping around to the beginning of the present row. to prevent address wrapping from occurring, the master must send a stop condition at the end of the page, then wait for the bus-free or eeprom-write time to elapse. then the master can generate a new start condition, and write the slave address byte (r/ w = 0) and the first memory address of the next memory row before continuing to write data. acknowledge polling: any time a eeprom byte is written, the ds3508 requires the eeprom write time (t w ) after the stop condition to write the contents of the byte to eeprom. during the eeprom write time, the device does not acknowledge its slave address because it is busy. it is possible to take advantage of this phenomenon by repeatedly addressing the ds3508, which allows communication to continue as soon as the ds3508 is ready. the alternative to acknowledge polling is to wait for a maximum period of t w to elapse before attempting to access the device. reading a single byte from a slave: unlike the write operation that uses the specified memory address byte to define where the data is to be written, the read opera- tion occurs at the present value of the memory address counter. to read a single byte from the slave, the master generates a start condition, writes the slave address byte with r/ w = 1, reads the data byte with a nack to indicate the end of the transfer, and generates a stop condition. however, since requiring the master to keep track of the memory address counter is impractical, the following method should be used to perform reads from a specified memory location. reading multiple bytes from a slave: the read opera- tion can be used to read multiple bytes with a single transfer. when reading bytes from the slave, the master simply acks the data byte if it desires to read another i 2 c, 8-channel gamma buffer with eeprom 12 ______________________________________________________________________________________
ds3508 i 2 c, 8-channel gamma buffer with eeprom ______________________________________________________________________________________ 13 byte before terminating the transaction. after the master reads the last byte it must nack to indicate the end of the transfer and generates a stop condition. manipulating the address counter for reads: a dummy write cycle can be used to force the address counter to a particular value. to do this the master gen- erates a start condition, writes the slave address byte (r/ w = 0), writes the memory address where it desires to read, generates a repeated start condi- tion, writes the slave address byte (r/ w = 1), reads data with ack or nack as applicable, and generates a stop condition. the master must nack the last byte to inform the slave that no additional bytes are to be read. applications information power-supply decoupling to achieve the best results when using the ds3508, decouple both power-supply pins (v cc and v dd ) with a 0.01? or 0.1? capacitor. use a high-quality ceramic surface-mount capacitor if possible. surface-mount components minimize lead inductance, which improves performance, and ceramic capacitors tend to have adequate high-frequency response for decoupling applications. sda and scl pullup resistors sda is an i/o with an open-collector output that requires a pullup resistor to realize high-logic levels. a master using either an open-collector output with a pullup resistor or a push-pull output driver can be used for scl. pullup resistor values should be chosen to ensure that the rise and fall times listed in the electrical characteristics are within specification. a typical value for the pullup resistors is 4.7k . slave address* start start 1 1 1 0 1 0 a0 r/w slave ack slave ack slave ack msb lsb msb lsb msb lsb read/ write register address b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 data stop single-byte write -write cr register to 80h single-byte read -read gm3 two-byte write - write gm1 and gm2 to 80h start repeated start e9h data master nack stop 11101000 02h 11101001 11101000 00001000 00000010 00000000 00000000 e8h 08h 80h stop gm3 example i 2 c transactions (when a0 is connected to gnd) typical i 2 c write transaction *the slave address is determined by address pin a0. 10000000 e8h a) b) c) slave ack slave ack slave ack slave ack slave ack slave ack start 11101000 e8h 00h stop 80h 1 000 0 0 00 slave ack slave ack slave ack 80h 1 0000000 slave ack two-byte read - read gm1 and gm2 d) start 11101000 e8h 00h stop slave ack slave ack slave ack master ack e9h 11101001 data data master nack repeated start gm1 gm2 figure 5. i 2 c communication examples package information (for the latest package outline information, go to www.maxim-ic.com/dallaspackinfo .) package type package code document no. 20 tssop 56-g2010-000
ds3508 i 2 c, 8-channel gamma buffer with eeprom maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 14 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2008 maxim integrated products is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 1/08 initial release. 1 3/08 in the nonvolatile memory characteristics table, removed t a = +25 c 200,000 write cycle specification for eeprom write cycles. 4

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